Applications of video encoding typically use a motion estimation and compensation mechanism. The motion estimation and compensation mechanism aids in compressing the video since each frame can be based on frames previously encoded. A decoder can reproduce the frame by copying each block from a reference frame according to one or a few motion vectors. Different blocks of the encoded frame can be encoded using the same data in the reference frame, so the data is largely reused. The reference frames are typically buffered in a double data rate (i.e., DDR) memory because of the large amount of information involved, especially in high-definition video. The large amount of data is commonly subject to inefficient read operations.
Current video decoding methods use a data cache to buffer some of the data stored in the DDR memory. The cached data supports reuse in the decoding process. However, cache mechanisms are expensive in terms of both silicon area and power. To support video decoding applications, a size of the cache is large. In addition, the timing control of large data caches is difficult.
Another common method used in video decoding involves direct memory access (i.e., DMA) reads from the DDR memory. The DMA reads have a disadvantage in that reuse of areas that were previously read are not supported. As such, the same data is fetched several times, which is expensive in terms of the data bus to and from the DDR memory since the amount of data is high.
It would be desirable to implement a system and method for adjusting direct memory access transfers used in decoding video.